Thus, by choosing a suitable type of memory, designers can improve the performance of the pipelined data path. Because of the natural structure of a pipeline, which typically reads values before it writes results, such hazards are rare. Pipelines for complex instruction sets that support autoincrement addressing and require operands to be read late in the pipeline could create a WAR hazards.
So when i2 is reading the contents of Register 1, register 1 still contains 6, not 3. In the following example, instruction 2 anti-depends on instruction 3 — the ordering of these instructions cannot be changed, nor can they be executed in parallel possibly changing the instruction orderingas this would affect the final value of A.
However, if i1 write 3 to register 1 does not fully exit the pipeline before i2 starts executing, it means that R1 does not contain the value 3 when i2 performs its addition.
This hazard occurs when there are some instructions that write results early in the instruction pipeline, and other instructions that read a source late in the pipeline.
Control hazards branch hazards [ edit ] To avoid control hazards microarchitectures can: insert a pipeline bubble discussed aboveguaranteed to increase latencyor use branch prediction and essentially make educated guesses about which instructions to insert, in which case a pipeline bubble will only be needed in the case of an incorrect prediction In the event that a branch causes a pipeline bubble after incorrect instructions have entered the pipeline, care must be taken to prevent any of the wrongly-loaded instructions from having any effect on the processor state excluding energy wasted processing them before they were discovered to be loaded incorrectly.